Speaking

This page contains a list of speaking engagements I’ve performed over the years, and their recordings, if available. I usually give presentations on my academic work and EDA/chip design in general.

If you would like me to speak at your event, please get in contact! I’m always honoured to be invited to speak on the topics of semiconductors, EDA and rad-hard design.

2026

• Slingshot and Slander: Tools for Analysing and Mutating SystemVerilog, Powered by Slang
  • Presented to: FOSSi DownUnderflow 2026
  • Recording: Very sadly, not recorded. Slides available here

2025

• Successes and Limitations in Automated TMR for Rad-Hard Designs (8 December 2025)
  • Presented to: Macquarie University Silicon Platforms Laboratory
  • Recording: Not recorded, slides available here
• YUG 11: Towards an Automated TMR EDA flow for Yosys by Matt Young (23 October 2025)
  • Presented to: YosysHQ Users Group (YUG)
  • Recording: https://www.youtube.com/watch?v=ZiIUKr-2IAE
• Digital Chip Design: Tools and Techniques (28 August 2025)
  • Presented to: UQ Computing Society
  • Recording: https://www.youtube.com/watch?v=kfinfHX5m0k
• TaMaRa: The Post Mortem (23 June 2025)
  • Presented to: Emesent Pty Ltd
  • Recording: Not available

2024

• Lunch and Learn: TaMaRa: An automated triple modular redundancy EDA flow for Yosys (8 August 2024)
  • Presented to: Emesent Pty Ltd
  • Recording: Not available

2023

• Lunch and Learn: Open3D vs PCL (24 January 2023)
  • Presented to: Emesent Pty Ltd
  • Recording: Not available