Projects
The following is a list of projects I’m working on, or have worked on.
Active projects
⚠️ These projects are “active” in the sense that I would work on them and they are not finished. However, as a poor little PhD student, I don’t have time to actively work on them.
Slingshot
Category: Computer engineering/EDA
Licence: Mozilla Public License v2.0 (weak copyleft)
Slingshot is a language server for the SystemVerilog hardware description language, with a focus on accurate multi-file completion. The overarching goal is to make SystemVerilog as intuitive to edit as C++ or Rust.
Compared to other SV LSPs, the main feature that Slingshot brings to the table is a completion-first approach, using the powerful Slang frontend. The intent is to provide fast, accurate and robust completion even in complex projects. The trade-off is this does mean that features such as “go-to-reference” take somewhat of a backseat.
Slingshot is (now) written in C++20. Previously, it was written in Kotlin and used ANTLR. This new rewrite aims to:
- Improve speed and utility by using a proper SystemVerilog parser (Slang)
- Reduce memory usage
SoCUte
Category: Embedded systems
Licence: Mozilla Public License v2.0 (weak copyleft)
SoCUte is a work in progress assembler for the Sega Saturn’s SCU (System Control Unit) DSP chip, written in Rust.
The SCU-DSP is poorly documented, notoriously hard to program chip with all sorts of quirks, running at 14.3 MHz. However, it does have some horsepower to it (at least, for its day).
The goal of SoCUte is to write a more modern and portable assembler for the SCU-DSP for the purposes of homebrew and experimenting, whilst maintaining 100% compatibility with original source files. Eventually, I’m hoping to turn this into a relatively advanced macro assembler that’s better than Sega’s official tool.
I’m hoping that one day myself or others will be able to use this tool to unlock more power from the Saturn.
Kural and EDTear
Category: Data and optimisation
Licence: ISC (permissive)
Kural and EDTear are each respectively tools I am writing in Rust to compute optimal trade routes, and collect trade data, for the video game Elite: Dangerous. EDTear records data from EDDN, which is basically a large ZeroMQ relay for E:D users. I record this data and insert it into a PostGIS enabled PostgreSQL database. Kural connects to this database, and uses integer linear programming to solve large-scale (i.e. galaxy-wide) instances of the bounded knapsack problem to compute optimal cargo hold layouts.
EDTear stands for the “E:D Trade Ear” (inspired by bear, the Build Ear), and Kural is named after the Tirukkuṟaḷ, an ancient Tamil language text that may be the first documented discovery of supply and demand.
View my blog for more details →
Past projects
TaMaRa (2025)
Category: Computer engineering/EDA
Licence: Mozilla Public License v2.0 (weak copyleft)
TaMaRa is an automated Triple Modular Redundancy EDA flow for the open-source Yosys EDA tool, designed to protect FPGAs and ASICs from Single Event Upsets in spaceflight and other harsh envionrments. There is some existing literature in this area, but TaMaRa is unique in that it’s integrated into Yosys directly, and has an extensive test suite using a combination of manual tests, formal verification and RTL fuzzing techniques.
In further detail, copied from my thesis’ description:
An automated triple modular redundancy EDA flow for Yosys
For safety-critical sectors such as aerospace and defence, silicon ICs and FPGA gateware must be designed to be fault tolerant in order to mitigate the effects of Single Event Upsets (SEUs) triggered by ionising radiation. One common fault-tolerant design technique is Triple Modular Redundancy (TMR), which mitigates SEUs by triplicating key parts of the design and using voter circuits to select a non-corrupted result if an SEU occurs. Typically, TMR is manually designed at the HDL level. However, this approach is an additional time-consuming and potentially error-prone step in the already complex design pipeline. Instead, I propose TaMaRa: a novel fully automated TMR flow for the open source Yosys EDA tool. TaMaRa will accept any Yosys-compatible HDL input, and use graph theory algorithms to synthesise a TMR netlist. I will also use a combination of formal methods and simulation to prove the correctness of the TMR flow.
TaMaRa was completed for my Bachelor of Computer Science (Honours) thesis at the University of Queensland, between July 2024 and June 2025.
I was kindly invited by Matt Venn of YosysHQ GmbH to write an official blog post for
them on the TaMaRa algorithm! You can read it here →
musicvis3d (2024)
Category: Computer graphics
Licence: ISC (permissive)
This is a semi real-time 3D audio visualisation using OpenGL. The visualisation consists of offline spectral data that is rendered in real-time in the form of 3D bars. A multitude of graphics techniques are used, including: quaternion camera animation, camera shake using Simplex noise under fractal Brownian motion, a skybox, and a post-processing stage that implements chromatic aberration. The application is written in a mix of C++ (for rendering) and Python (for DSP). The spectrum of bars is computed using the Fast Fourier Transform.
I implemented this for the course COSC3000 at UQ, in 2024; as part of my BCompSc undergraduate degree.
Hermes/Atlas (2023)
Category: Computer graphics, data and optimisation
Licence: Mozilla Public License v2.0 (weak copyleft)
Hermes/Atlas is a custom simulator and 3D renderer for Brisbane’s public transport network. It was written for our DECO3801 capstone group project during my BCompSc degree at UQ, in 2023.
I was responsible for the renderer (“Atlas”), which is built on top of the libGDX framework in Kotlin. The main features of Atlas are:
- Multi-threaded rendering architecture that allows for efficient streaming of network resources (OpenStreetMap raster tiles) without blocking
- Dynamically queries and extrudes PostGIS building polygons into plausible 3D building models
- Optimisations: distance culling, frustum culling, 2-tier LoD system
- Custom garbage collected cache data structure for managing a large number of map tiles efficiently
- First-person camera controller
- Cross-platform: Windows, Mac and Linux
- I was also responsible for Dockerizing and importing offline OpenStreetMap data
Visited the Hermes/Atlas repository →
HPC Ant colony simulator (2022)
Category: High performance computing
Licence: MPL 2.0 (weak copyleft)
I implemented a high-performance, biologically-inspired ant simulator in C++. I compared and contrasted a naive serial implementation against two HPC implementations, using OpenMP and MPI respectively. I also deployed the program using Slurm to UQ’s getafix HPC student cluster. As part of this work, I came up with a “SnapGrid” (snapshot grid) data structure that is used to implement thread-safe updates for the OpenMP/MPI version. Finally, I performed extensive performance profiling using Cachegrind.
This was done for the course COSC3500 at UQ, in 2022; as part of my BCompSc undergraduate degree.
Visit the ant-colony-hpc repo →
Open-source contributions
You’ll find me around the place contributing to free and open-source software where I can. Most of the contributions I do nowadays relate to FOSS EDA tools for ASIC design.
EDA
- My main focus at the moment is LibreLane, e.g. adding PEX capability
- I helped a bit with IIC-OSIC-TOOLS, Yosys and slang-server
Archiving
- I purchased and scanned the user manual for the JVC GR-AX2U Compact-VHS camcorder, which I uploaded to the
Internet Archive (or on my site
here if you prefer)
- My understanding is that this is the only copy of it on the entire Internet!
Others
- I patched Intel’s media-driver to fix a segfault.
- I contributed new game features to edsm-dumps-model, a Rust Serde model for Elite: Dangerous Star Map JSON dumps